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| HT1621 ram mapping 32 4 lcd controller for i/o c selection table ht162x ht1620 HT1621 ht1622 ht16220 ht1623 ht1625 ht1626 ht1627 ht16270 com 4 4 8888161616 seg 32 32 32 32 48 64 48 64 64 built-in osc. crystal osc. 1 april 21, 2000 features operating voltage : 2.4v~5.2v built-in 256khz rc oscillator external 32.768khz crystal or 256khz frequency source input selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty lcd applications internal time base frequency sources two selectable buzzer frequencies (2khz/4khz) power down command reduces power consumption built-in time base generator and wdt time base or wdt overflow output 8 kinds of time base/wdt clock sources 32 4 lcd driver built-in 32 4 bit display ram 3-wire serial interface internal lcd driving frequency source software configuration feature data mode and command mode instructions r/w address auto increment three data accessing modes vlcd pin for adjusting lcd operating voltage general description the HT1621 is a 128 pattern (32 4), memory mapping, and multi-function lcd driver. the s/w configuration feature of the HT1621 makes it suitable for multiple lcd applica - tions including lcd modules and display sub- systems. only three or four lines are required for the interface between the host controller and the HT1621. the HT1621 contains a power down command to reduce power consumption.
block diagram note: cs : chip selection bz, bz : tone outputs wr ,rd , data: serial interface com0~com3, seg0~seg31: lcd outputs irq : time base or wdt overflow output HT1621 2 april 21, 2000 ! " # $ " $ #% & ' ( ( ! ) * * * pin assignment HT1621 3 april 21, 2000 $ + $ , $ - $ . $ # $ / $ % $ " * 0 ! * * ! ) ( ( " % / # $ 1 $ 2 $ %" $ %% $ %/ $ %# $ %. $ %- $ %, $ %+ $ %1 $ %2 $ /" $ /% $ // $ /# $ /. $ /- $ /, $ /+ $ /1 $ /2 $ #" $ #% $ + $ , $ - $ . $ # $ / $ % $ " * ! * * ! ) ( ( " % / # $ 1 $ 2 $ %" $ %% $ %/ $ %# $ %. $ %- $ %, $ %+ $ %1 $ %2 $ /" $ /% $ // $ /# $ /. $ /- $ /, $ /+ $ /1 $ /2 $ #" $ #% .1 .+ ., .- .. .# ./ .% ." #2 #1 #+ #, #- #. ## #/ #% #" /2 /1 /+ /, /- % / # . - , + 1 2 %" %% %/ %# %. %- %, %+ %1 %2 /" /% // /# /. .1 .+ ., .- .. .# ./ .% ." #2 #1 #+ #, #- #. ## #/ #% #" /2 /1 /+ /, /- % / # . - , + 1 2 %" %% %/ %# %. %- %, %+ %1 %2 /" /% // /# /. $ - $ # $ % * * * ! ) ( " % $ + $ 2 $ %% $ %# $ %- $ %+ $ %2 $ /% $ /# $ /- $ /+ $ /2 $ #% / /1 /+ /, /- /. /# // /% /" %2 %1 %+ %, %- % / # . - , + 1 2 %" %% %/ %# %. pad assignment chip size: 127 129 (mil) 2 * the ic substrate should be connected to vdd in the pcb layout artwork. HT1621 4 april 21, 2000 ! ) ( % / # . - , + 1 2 %" %% %/ %# %. %- %, %+ %1 %2 /" /% // /# /. /- /, /+ /1 /2 #" #% #/ ## #. #- #, #+ #1 #2 ." .% ./ .# .. .- ., .+ .1 3" 4" 5 * ! * * ( " % / # $ #% $ #" $ /2 $ /1 $ /+ $ /, $ /- $ /. $ /# $ // $ /% $ /" $ %2 $ %1 $ %+ $ %, $ %- $ %. $ %# $ %/ $ %% $ %" $ 2 $ 1 $ + $ , $ - $ . $ # $ / $ % $ " pad coordinates unit:mil pad no. x y pad no. x y 1 55.04 59.46 25 58.14 25.29 2 58.52 22.18 26 58.14 18.66 3 58.52 15.56 27 58.14 11.94 4 58.52 5.36 28 58.14 5.31 5 58.52 4.51 29 58.14 1.32 6 58.52 11.14 30 58.14 7.95 7 58.52 34.76 31 58.14 14.58 8 58.52 41.90 32 58.14 21.21 9 58.52 49.13 33 55.55 59.46 10 58.52 59.08 34 48.92 59.46 11 44.07 59.08 35 42.29 59.46 12 31.58 59.08 36 35.66 59.46 13 20.70 59.08 37 29.03 59.46 14 13.98 59.08 38 22.40 59.46 15 7.05 59.08 39 15.77 59.46 16 0.34 59.08 40 9.14 59.46 17 6.33 59.08 41 2.42 59.46 18 12.96 59.08 42 4.21 59.46 19 19.59 59.08 43 10.84 59.46 20 58.14 58.44 44 17.47 59.46 21 58.14 51.81 45 24.10 59.46 22 58.14 45.18 46 30.73 59.46 23 58.14 38.55 47 38.17 59.46 24 58.14 31.92 48 45.39 59.46 HT1621 5 april 21, 2000 pad description pad no. pad name i/o function 1cs i chip selection input with pull-high resistor when the cs is logic high, the data and command read from or written to the HT1621 are disabled. the serial interface circuit is also reset. but if cs is at logic low level and is input to the cs pad, the data and command transmission between the host con - troller and the HT1621 are all enabled. 2rd i read clock input with pull-high resistor data in the ram of the HT1621 are clocked out on the falling edge of the rd signal. the clocked out data will appear on the data line. the host controller can use the next rising edge to latch the clocked out data. 3wr i write clock input with pull-high resistor data on the data line are latched into the HT1621 on the ris - ing edge of the wr signal. 4 data i/o serial data input/output with pull-high resistor 5 vss negative power supply, ground 7 osci i the osci and osco pads are connected to a 32.768khz crystal in order to generate a system clock. if the system clock comes from an external clock source, the external clock source should be connected to the osci pad. but if an on-chip rc oscillator is selected instead, the osci and osco pads can be left open. 6 osco o 8 vlcd i lcd power input 9 vdd positive power supply 10 irq o time base or wdt overflow flag, nmos open drain output 11, 12 bz, bz o 2khz or 4khz tone frequency output pair 13~16 com0~com3 o lcd common outputs 48~17 seg0~seg31 o lcd segment outputs absolute maximum ratings supply voltage ................................. 0.3v~5.5v storage temperature.................... 50 o c~125 o c input voltage ....................v ss 0.3v~v dd +0.3v operating temperature.................. 25 o c~75 o c note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this de - vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT1621 6 april 21, 2000 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.4 5.2 v i dd1 operating current 3v no load/lcd on on-chip rc oscillator 150 300 a 5v 300 600 a i dd2 operating current 3v no load/lcd on crystal oscillator 60 120 a 5v 120 240 a i dd3 operating current 3v no load/lcd on external clock source 100 200 a 5v 200 400 a i stb standby current 3v no load power down mode 0.1 5 a 5v 0.3 10 a v il input low voltage 3v data, wr ,cs ,rd 0 0.6 v 5v 0 1.0 v v ih input high voltage 3v data, wr ,cs ,rd 2.4 3.0 v 5v 4.0 5.0 v i ol1 data, bz, bz , irq 3v v ol =0.3v 0.5 1.2 ma 5v v ol =0.5v 1.3 2.6 ma i oh1 data, bz, bz 3v v oh =2.7v 0.4 0.8 ma 5v v oh =4.5v 0.9 1.8 ma i ol2 lcd common sink current 3v v ol =0.3v 80 150 a 5v v ol =0.5v 150 250 a i oh2 lcd common source current 3v v oh =2.7v 80 120 a 5v v oh =4.5v 120 200 a i ol3 lcd segment sink current 3v v ol =0.3v 60 120 a 5v v ol =0.5v 120 200 a i oh3 lcd segment source current 3v v oh =2.7v 40 70 a 5v v oh =4.5v 70 100 a r ph pull-high resistor 3v data, wr ,cs ,rd 40 80 150 k 5v 30 60 100 k HT1621 7 april 21, 2000 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock 3v on-chip rc oscillator 256 khz 5v 256 khz f sys2 system clock 3v crystal oscillator 32.768 khz 5v 32.768 khz f sys3 system clock 3v external clock source 256 khz 5v 256 khz f lcd lcd clock on-chip rc oscillator f sys1 /1024 hz crystal oscillator f sys2 /128 hz external clock source f sys3 /1024 hz t com lcd common period n: number of com n/f lcd s f clk1 serial data clock (wr pin) 3v duty cycle 50% 150 khz 5v 300 khz f clk2 serial data clock (rd pin) 3v duty cycle 50% 75 khz 5v 150 khz f tone tone frequency on-chip rc oscillator 2.0 or 4.0 khz t cs serial interface reset pulse width (figure 3) cs 250 ns t clk wr ,rd input pulse width (figure 1) 3v write mode 3.34 s read mode 6.67 5v write mode 1.67 s read mode 3.34 t r ,t f rise/fall time serial data clock width (figure 1) 3v 120 ns 5v t su setup time for data to wr , rd clock width (figure 2) 3v 120 ns 5v t h hold time for data to wr , rd clock width (figure 2) 3v 120 ns 5v t su1 setup time for cs to wr ,rd clock width (figure 3) 3v 100 ns 5v t h1 hold time for cs to wr ,rd clock width (figure 3) 3v 100 ns 5v HT1621 8 april 21, 2000 HT1621 9 april 21, 2000 functional description display memory ram the static display memory (ram) is organized into 32 4 bits and stores the displayed data. the contents of the ram are directly mapped to the contents of the lcd driver. data in the ram can be accessed by the read, write, and read-modify-write commands. the following is a mapping from the ram to the lcd pattern: system oscillator the HT1621 system clock is used to generate the time base/watchdog timer (wdt) clock fre - quency, lcd driving clock, and tone frequency. the source of the clock may be from an on-chip rc oscillator (256khz), a crystal oscillator (32.768khz), or an external 256khz clock by the s/w setting. the configuration of the sys- tem oscillator is as shown. after the sys dis command is executed, the system clock will stop and the lcd bias generator will turn off. that command is, however, available only for the on-chip rc oscillator or for the crystal oscil- lator. once the system clock stops, the lcd dis- play will become blank, and the time base/wdt lose its function as well. the lcd off command is used to turn the lcd bias generator off. after the lcd bias gen - erator switches off by issuing the lcd off command, using the sys dis command re - duces power consumption, serving as a system power down command. but if the external clock source is chosen as the system clock, using the sys dis command can neither turn the oscilla - tor off nor carry out the power down mode. the crystal oscillator option can be applied to con - nect an external frequency source of 32khz to the osci pin. in this case, the system fails to $ " $ % $ / $ # $ #% " % / # # / % " #% " % / # , 6 3 - 4 . 4 7774 " 5 . 6 3 #4 /4 %4 "5 ram mapping 2"8 -"8 %"8 0 4 9 : ; ; * figure 1 -"8 *! -"8 4 9 0 * * 0 figure 2 0 -"8 -"8 &! 9 9 0 4 9 % % * * figure 3 HT1621 10 april 21, 2000 enter the power down mode, similar to the case in the external 256khz clock source operation. at the initial system power on, the HT1621 is at the sys dis state. time base and watchdog timer (wdt) the time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. the watch dog timer (wdt), on the other hand, is com - posed of an 8-stage time base generator along with a 2-stage count-up counter, and is de - signed to break the host controller or other sub - systems from abnormal states such as unknown or unwanted jump, execution errors, etc. the wdt time-out will result in the setting of an internal wdt time-out flag. the outputs of the time base generator and of the wdt time-out flag can be connected to the irq out - put by a command option. there are totally eight frequency sources available for the time base generator and the wdt clock. the fre - quency is calculated by the following equation. f wdt = 32khz 2 n where the value of n ranges from 0 to 7 by com - mand options. the 32khz in the above equation indicates that the source of the system fre - quency is derived from a crystal oscillator of 32.768khz, an on-chip oscillator (256khz), or an external frequency of 256khz. if an on-chip oscillator (256khz) or an external 256khz frequency is chosen as the source of the system frequency, the frequency source is by de - fault prescaled to 32khz by a 3-stage prescaler. employing both the time base generator and the wdt related commands, one should be careful since the time base generator and wdt share the same 8-stage counter. for example, invoking the wdt dis command disables the time base generator whereas executing the wdt en command not only enables the time base generator but activates the wdt time-out flag output (connect the wdt time-out flag to the irq pin). after the timer en command is transferred, the wdt is disconnected from the irq pin, and the output of the time base generator is connected to the irq pin. the wdt can be cleared by executing the clr wdt command, and the contents of the time base generator is cleared by executing the clr wdt or the clr % 1 ! #/+,1< = $ > 9 /-,9< = ? /-,9< = 9 system oscillator configuration ! $ $0 ! $ 0 ! * ! ) ! ) $ 0 ! ; ) 9 :@#/9< = /-, . 9 / @"a+ timer and wdt configurations HT1621 11 april 21, 2000 timer command. the clr wdt or the clr timer command should be executed prior to the wdt en or the timer en command re - spectively. before executing the irq en com - mand the clr wdt or clr timer command should be executed first. the clr timer com - mand has to be executed before switching from the wdt mode to the time base mode. once the wdt time-out occurs, the irq pin will stay at a logic low level until the clr wdt or the irq dis command is issued. after the irq output is disabled the irq pin will remain at the floating state. the irq output can be enabled or dis - abled by executing the irq en or the irq dis command, respectively. the irq en makes the output of the time base generator or of the wdt time-out flag appear on the irq pin. the config- uration of the time base generator along with the wdt are as shown. in the case of on-chip rc oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. at the power down mode the time base/wdt loses all its functions. on the other hand, if an external clock is se - lected as the source of system frequency the sys dis command turns out invalid and the power down mode fails to be carried out. that is, after the external clock source is selected, the HT1621 will continue working until system power fails or the external clock source is re - moved. after the system power on, the irq will be disabled. tone output a simple tone generator is implemented in the HT1621. the tone generator can output a pair of differential driving signals on the bz and bz, which are used to generate a single tone. by ex - ecuting the tone4k and tone2k commands there are two tone frequency outputs selectable. the tone4k and tone2k com - mands set the tone frequency to 4khz and 2khz, respectively. the tone output can be turned on or off by invoking the tone on or the tone off command. the tone outputs, namely bz and bz , are a pair of differential driving outputs used to drive a piezo buzzer. once the system is disabled or the tone output is inhibited, the bz and the bz outputs will re- main at low level. lcd driver the HT1621 is a 128 (32 4) pattern lcd driver. it can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of lcd driver by the s/w configu- ration. this feature makes the HT1621 suitable for multiply lcd applications. the lcd driving clock is derived from the system clock. the value of the driving clock is always 256hz even when it is at a 32.768khz crystal oscillator frequency, an on-chip rc oscillator frequency, or an external frequency. the lcd corresponding commands are summarized in the table. the bold form o f100, namely 100 , indicates the command mode id. if successive commands have been issued, the command mode id except for the first command, will be omitted. the lcd name command code function lcd off 100 00000010x turn off lcd outputs lcd on 100 00000011x turn on lcd outputs bias & com 100 0010abxcx c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option HT1621 12 april 21, 2000 off command turns the lcd display off by dis - abling the lcd bias generator. the lcd on command, on the other hand, turns the lcd display on by enabling the lcd bias generator. the bias and com are the lcd panel related commands. using the lcd related commands, the HT1621 can be compatible with most types of lcd panels. command format the HT1621 can be configured by the s/w set - ting. there are two mode commands to configure the HT1621 resources and to transfer the lcd display data. the configuration mode of the HT1621 is called command mode, and its com - mand mode id is 100 . the command mode con - sists of a system configuration command, a system frequency selection command, a lcd con - figuration command, a tone frequency selection command, a timer/wdt setting command, and an operating command. the data mode, on the other hand, includes read, write, and read-modify-write operations. the follow - ing are the data mode ids and the command mode id: operation mode id read data 1 1 0 write data 1 0 1 read-modify-write data 1 0 1 command command 1 0 0 the mode command should be issued before the data or command is transferred. if successive commands have been issued, the command mode id, namely 100 , can be omitted. while the system is operating in the non-successive command or the non-successive address data mode, the cs pin should be set to "1" and the previous operation mode will be reset also. once the cs pin returns to "0" a new operation mode id should be issued first. interfacing only four lines are required to interface with the HT1621. the cs line is used to initialize the serial interface circuit and to terminate the com - munication between the host controller and the HT1621. if the cs pin is set to 1, the data and command issued between the host controller and the HT1621 are first disabled and then initial - ized. before issuing a mode command or mode switching, a high level pulse is required to initial - ize the serial interface of the HT1621. the data line is the serial data input/output line. data to be read or written or commands to be written have to be passed through the data line. the rd line is the read clock input. data in the ram are clocked out on the falling edge of the rd sig - nal, and the clocked out data will then appear on the data line. it is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the rd signal. the wr line is the write clock input. the data, address, and command on the data line are all clocked into the HT1621 on the rising edge of the wr signal. there is an optional irq line to be used as an interface between the host controller and the HT1621. the irq pin can be selected as a timer output or a wdt overflow flag output by the s/w setting. the host control- ler can perform the time base or the wdt func- tion by being connected with the irq pin of the HT1621. timing diagrams read mode (command cod e:110) read mode (successive address reading) HT1621 13 april 21, 2000 % % "- . # / % " " % / # % 3 %5 3 /5 % % "- . # / % " " % / # 3 %5 / 3 /5 % % "- . # / % " " % / # 3 5 3 5 " % / # " % / # " % / # " 3 b % 5 3 b / 5 3 b # 5 write mode (command cod e:101) write mode (successive address writing) HT1621 14 april 21, 2000 % " %- . # / % " " % / # % 3 %5 3 %5 % " %- . # / % " " % / # / 3 /5 3 /5 % " %- . # / % " " % / # 3 5 3 5 " % / # " % / # " % / # " 3 b % 5 3 b / 5 3 b # 5 read-modify-write mode (command cod e:101) read-modify-write mode (successive address accessing) HT1621 15 april 21, 2000 % " %- . # / % " " % / # % 3 %5 3 %5 - . # / % " " % / # / 3 /5 3 /5 % " % " % / # 3 % 5 % " %- . # / % " " % / # 3 5 3 5 " % / # " % / # " % / # " 3 5 3 b % 5 3 b % 5 % / # " 3 b / 5 command mode (command cod e:100) mode (data and command mode) note: it is recommended that the host controller should read in the data from the data line between the rising edge of the rd line and the falling edge of the next rd line. HT1621 16 april 21, 2000 % " "1 + , - . # / % " % 1 + , - . # / % " 777 c application circuits host controller with an HT1621 display system note: the connection of irq and rd pin can be selected depending on the requirement of the c. the voltage applied to v lcd pin must be lower than v dd . adjust vr to fit lcd display, at v dd =5v, v lcd =4v, vr=15k 20%. adjust r (external pull-high resistance) to fit user s time base clock. HT1621 17 april 21, 2000 ! ) ? ! 9 $ > 9 % $ > 9 / #/+,1< = ( ( " a # $ "a $ #% d = % / % # e % /4 % # % . * * * command summary HT1621 18 april 21, 2000 name id command code d/c function def. read 110 a5a4a3a2a1a0d0d1d2d3 d read data from the ram write 101 a5a4a3a2a1a0d0d1d2d3 d write data to the ram read- modify- write 101 a5a4a3a2a1a0d0d1d2d3 d read and write to the ram sys dis 100 0000-0000-x c turn off both system oscillator and lcd bias generator yes sys en 100 0000-0001-x c turn on system oscillator lcd off 100 0000-0010-x c turn off lcd bias generator yes lcd on 100 0000-0011-x c turn on lcd bias generator timer dis 100 0000-0100-x c disable time base output wdt dis 100 0000-0101-x c disable wdt time-out flag output timer en 100 0000-0110-x c enable time base output wdt en 100 0000-0111-x c enable wdt time-out flag output tone off 100 0000-1000-x c turn off tone outputs yes tone on 100 0000-1001-x c turn on tone outputs clr timer 100 0000-11xx-x c clear the contents of time base generator clr wdt 100 0000-111x-x c clear the contents of wdt stage xtal 32k 100 0001-01xx-x c system clock source, crystal oscillator rc 256k 100 0001-10xx-x c system clock source, on-chip rc oscillator yes ext 256k 100 0001-11xx-x c system clock source, external clock source bias 1/2 100 0010-abx0-x c lcd 1/2 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option bias 1/3 100 0010-abx1-x c lcd 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option tone 4k 100 010x-xxxx-x c tone frequency, 4khz tone 2k 100 011x-xxxx-x c tone frequency, 2khz irq dis 100 100x-0xxx-x c disable irq output yes HT1621 19 april 21, 2000 name id command code d/c function def. irq en 100 100x-1xxx-x c enable irq output f1 100 101x-x000-x c time base/wdt clock output:1hz the wdt time-out flag after: 4s f2 100 101x-x001-x c time base/wdt clock output:2hz the wdt time-out flag after: 2s f4 100 101x-x010-x c time base/wdt clock output:4hz the wdt time-out flag after: 1s f8 100 101x-x011-x c time base/wdt clock output:8hz the wdt time-out flag after: 1/2 s f16 100 101x-x100-x c time base/wdt clock output:16hz the wdt time-out flag after: 1/4 s f32 100 101x-x101-x c time base/wdt clock output:32hz the wdt time-out flag after: 1/8 s f64 100 101x-x110-x c time base/wdt clock output:64hz the wdt time-out flag after: 1/16 s f128 100 101x-x111-x c time base/wdt clock output:128hz the wdt time-out flag after: 1/32 s yes test 100 1110-0000-x c test mode, user don't use. normal 100 1110-0011-x c normal mode yes note: x : don , t care a5~a0 : ram addresses d3~d0 : ram data d/c : data/command mode def. : power on reset default all the bold forms, namely 110 , 101 , and 100 , are mode commands. of these, 100 indicates the command mode id. if successive commands have been issued, the command mode id ex - cept for the first command will be omitted. the source of the tone frequency and of the time base/wdt clock frequency can be derived from an on-chip 256khz rc oscillator, a 32.768khz crystal oscillator, or an external 256khz clock. calculation of the frequency is based on the system frequency sources as stated above. it is recommended that the host controller should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1621. HT1621 20 april 21, 2000 copyright 2000 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 5f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 |
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